PIC16F873T-04E/SO【PDF 184/218 页】IC MCU FLASH 4KX14 EE 28SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3889

180页 181页 182页 183页 [184页]185页 186页 187页 188页

PIC16F87X

DS30292C-page 66

2001 Microchip Technology Inc.

REGISTER 9-1:

SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

bit 7

SMP: Sample bit

SPI Master mode:

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in slave mode

In I2C Master or Slave mode:

= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

= Slew rate control enabled for high speed mode (400 kHz)

bit 6

CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3 and Figure 9-4)

SPI mode:

For CKP = 0

= Data transmitted on rising edge of SCK

= Data transmitted on falling edge of SCK

For CKP = 1

= Data transmitted on falling edge of SCK

= Data transmitted on rising edge of SCK

In I2C Master or Slave mode:

= Input levels conform to SMBus spec

= Input levels conform to I2C specs

bit 5

D/A: Data/Address bit (I2C mode only)

= Indicates that the last byte received or transmitted was data

= Indicates that the last byte received or transmitted was address

bit 4

P: STOP bit

(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)

= STOP bit was not detected last

bit 3

S: START bit

(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)

= START bit was not detected last

bit 2

R/W: Read/Write bit Information (I2C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next START bit, STOP bit or not ACK bit.

In I2C Slave mode:

= Read

= Write

In I2C Master mode:

= Transmit is in progress

= Transmit is not in progress

Logical OR of this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.

bit 1

UA: Update Address (10-bit I2C mode only)

= Indicates that the user needs to update the address in the SSPADD register

= Address does not need to be updated

bit

BF: Buffer Full Status bit

Receive (SPI and I2C modes):

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

Transmit (I2C mode only):

= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full

= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式